The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
An integrated circuit layout, also referred to as an IC layout, mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. An IC layout is generated after numerous steps of an IC design, also called a “data preparation stage,” and a series of checks in a process, called “physical verification,” at the end. The most common checks in this verification process are design rule checking (DRC), layout versus schematic (LVS), parasitic extraction, antenna rule checking, and electrical rule checking (ERC). When all verification is complete, the data in the IC layout is translated into an industry standard format, typically a vector-based format, such as GDSII or OASIS, and sent to a semiconductor foundry, called a fab house. The foundry then converts, via mask data preparation (MDP) procedure, the data into a set of instructions by which a photomask writer can generate a physical mask (a photomask) to be used in a photolithographic process of semiconductor device fabrication. More recent MDP procedures require the additional steps associated with design for manufacturability such as, resolution enhancement technologies (RET) and optical proximity correction (OPC). By using a series of photomasks, in addition to other processes, a wafer having one or more die (chips) is fabricated.
In order to ensure the fabrication processes are functioning properly, it is important to examine or test a wafer or dies for any defects or deficiencies before they are turned into finished devices. Some defects or deficiencies can be attributed to a semiconductor process, and some can be attributed to a defect or deficiency on one or more of the photomasks. Thus, it is often important to determine where on an IC design layout that particular defect of deficiency is located. When using a standard process, the behavior of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes in the IC layout. A layout designer's job is to place and connect all the components that make up a chip so that they meet all criteria such as performance, size, and manufacturability. Therefore, an inadequately designed layout in the data preparation stage may cause a defect or deficiency in semiconductor devices on a wafer or die in fabrication stage.
For this reason, in many cases it is needed to exactly locate a particular pattern on an IC layout, which may be responsible for some defect or deficiency observed on a wafer or die. The location information of that particular pattern may be obtained from various known metrology tools, which, however, may not be accurate enough. For more accurate location information of a particular pattern, SEM (Scanning Electron Microscope) pictures, directly taken from a die or wafer, may be used to provide image information. In many occasions, however, such image information from SEM pictures is still limited in its ability to provide precise location information of a particular pattern if the area on an IC layout that is being examined and searched is filled with similar looking patterns, such as CMP (chemical mechanical polishing/planarization) dummy features, and the particular pattern shown on the SEM picture happens to be one of them. Since dummy features are identical through entire field of view or even through entire die, to distinguish a group of dummy features or patterns by image information from SEM pictures alone is extremely difficult and virtually impossible.
Accordingly, what is needed is a method to generate patterns that contains encoded visual distinctions that would be carried into photomasks, wafers, and dies so that when there is a need to locate a particular pattern on the layout from image information, such as SEM pictures, it can be more-quickly and easily located via a specific encoded distinction.